Method and apparatus for testing a device in an electronic component

ABSTRACT

A method and apparatus is disclosed for testing a reconfigurable logic block. Preferably, this invention is intended to be used with Field Programmable Gate Array. According to the invention, a test bus addressing unit and a test bus activation unit are used to perform a test on a logic block. Upon selection of a corresponding logic block, a test data is outputted on a test bus which enables a testing of the logic function.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This patent application claims priority of U.S. provisionalpatent application No. 60/425721, filed Nov. 13, 2002 and entitled“Method and apparatus for testing a device in an electronic component”and of International patent application No. IB/02/04696 entitled “Methodand apparatus for testing a device in an electronic component” and filedNov. 10, 2002.

TECHNICAL FIELD

[0002] This invention pertains to the field of electronics; moreprecisely, this invention relates to the field of testing processingblocks.

BACKGROUND OF THE INVENTION

[0003] Integrated circuits may be defined as three different classes.

[0004] A first class of integrated circuits comprises analog circuits,while a second class of integrated circuits comprises digital circuitsand a third class of integrated circuit comprises mixed circuits.

[0005] Analog circuits are circuits which comprise inputs, outputs andprocessing that are strictly of the analog type. An operationalamplifier belongs to this first class of integrated circuits.

[0006] Digital circuits are circuits whose inputs, outputs andprocessing are strictly of the digital type. For instance, Random AccessMemory (RAM) and microprocessors belong to this second class ofintegrated circuits.

[0007] Mixed circuits comprise both analog and digital inputs andoutputs with usually digital processing. For instance, analog to digitalconverter and fiber optics transceiver belong to this third class.

[0008] Recent observations indicate that in all the above-mentionedclasses, current integration trends see a doubling of the number ofelements in a circuit every two year.

[0009] On the other hand, the number of inputs and outputs in a circuitdoubles every five years.

[0010] As a consequence, this leads to an increasingly greater number ofinternal nodes and complex circuitry with little or no access to theinput/output ports.

[0011] It will therefore be appreciated by someone skilled in the artthat such a situation increases tasks related to the debugging of acircuit comprising these internal nodes and complex circuitry.

[0012] While someone skilled in the art will appreciate that this isespecially true in the domain of reconfigurable devices such as FieldProgrammable Gate Array (FPGA), it will also be appreciated that suchlimitations are also met in other types of electronic componentsimplementing a processing function such as non-logic circuits. In anycases, it is highly desirable to be able to isolate and test everyresources of a processing block in an electronic component.

[0013] Common methods used to isolate and test every resource of theFPGA rely on traditional FPGA design tools and often necessitate areprogramming of the FPGA in order to implement a chosen testingfunction. In some cases, reprogramming of the FPGA can take a largeamount of time.

[0014] Some tools have been recently developed by FPGA manufacturers toprovide a probe at a selected point of the FPGA to provide its value toan output of the FPGA by appropriate FPGA programming. Someone skilledin the art will appreciate that while such a feature may help a designerto locate potential errors, it does not provide an efficient toolkit totest every resources of the FPGA.

[0015] In fact, as the number of outputs of the FPGA is limited, thepotential number of probe points is also limited.

[0016] There is therefore a need to overcome the above-mentioneddrawbacks.

SUMMARY OF THE INVENTION

[0017] It is an object of the invention to provide an apparatus fortesting a plurality of devices in a field programmable gate array.

[0018] Yet another object of the invention is to provide an apparatusfor testing a plurality of devices in an electronic component.

[0019] It is another object of the invention to provide a method fortesting a plurality of devices in an electronic component.

[0020] Yet another object of the invention is to provide a method fortesting a plurality of devices in a field programmable gate array.

[0021] According to one aspect of the invention, there is provided amethod for testing a plurality of devices in an electronic component,the method comprising the steps of receiving a plurality of data signalsfrom a plurality of devices to test, each of the plurality of devices totest receiving an input signal and providing a data signal in accordancewith a device function, selecting at least one of the received pluralityof data signals in accordance with a device selection signal, andproviding the selected data signals on a test bus, whereby the selectionof at least one of the received plurality of data signals on a test busenables a testing of a plurality of devices.

[0022] According to another aspect of the invention, there is providedan apparatus for testing at least one device in an electronic component,each of the at least one device of the electronic component receiving aninput signal and providing an output signal in accordance with a devicefunction, the electronic component comprising a plurality of devices,the apparatus comprising a data signal selecting unit, receiving a datasignal outputted from a device in response to an input signal providedto the device, and providing the data signal in accordance with aselection signal and a test bus, receiving the data signal from the dataselecting unit and outputting the data signal on an output of theelectronic component.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Further features and advantages of the present invention willbecome apparent from the following detailed description, taken incombination with the appended drawings, in which:

[0024]FIG. 1 is a flow chart which shows the preferred embodiment of theinvention; a plurality of test points are selected in a design to test;a corresponding address is then attributed to each of the selected testpoints and a corresponding address decoder and a test bus activationunit are inserted for each of the selected test points;

[0025]FIG. 2 is a block diagram which shows two embodiments of theinvention; in one embodiment, a test bus general structure is provided,in another embodiment, a stimulus bus test is provided;

[0026]FIG. 3 is a block diagram which shows another embodiment of theinvention; in this embodiment, the test bus is unclocked;

[0027]FIG. 4 is a block diagram which shows another embodiment of theinvention; in this embodiment, a shared test bus is clocked by a singleclock signal;

[0028]FIG. 5 is a block diagram which shows another embodiment of theinvention; in this embodiment, a shared bus is clocked by a plurality ofclock signals;

[0029]FIG. 6 is a block diagram which shows another embodiment of theinvention; in this embodiment, a plurality of test buses are clocked bya plurality of clock signals;

[0030]FIG. 7 is a block diagram which shows another embodiment of theinvention; in this embodiment, a plurality of test buses are clocked bya single clock signal; and

[0031]FIG. 8 is a block diagram which shows another embodiment of theinvention; in this embodiment a plurality of shared test buses areclocked by a plurality of clock signals.

[0032] It will be noted that throughout the appended drawings, likefeatures are identified by like reference numerals.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0033] Now referring to FIG. 1, there is shown the preferred embodimentof the invention.

[0034] According to step 2, a plurality of test points are selected inan electronic component. In one embodiment of the invention, each of theselected plurality of test points is preferably located at an output ofa processing block to test; in the preferred embodiment, the pluralityof test points are located inside the processing block to test, in orderto probe an internal element of the processing block. The processingblock is implementing a processing function. These test points areselected in accordance with a user choice.

[0035] It will be appreciated that the processing block may be locatedin any one of an analog circuit, a digital circuit and a mixed circuit.In the case of a digital circuit the processing block may be a logicbloc.

[0036] According to step 4, and still in the preferred embodiment of theinvention, an address, identifying a test point of the plurality of testpoints, is attached to each of the plurality of selected test points.

[0037] The address is preferably a base-2 type address. In anotherembodiment, any other type of addressing scheme may be used to identifya test point. Still in the preferred embodiment of the invention, theaddress attached to each of the selected test points is unique.

[0038] According to step 6 of FIG. 1, a corresponding address decoderand a test bus activation unit is inserted in the design of theelectronic component for each of the selected test points as explainedbelow.

[0039] The corresponding address decoder is responsible for providing anactivation signal to the test bus activation unit if a test addresssignal provided to the address decoder refers to the corresponding testaddress of the decoder.

[0040] In the case where the electronic component is a FieldProgrammable Gate Array (FPGA), the design of the FPGA (i.e. layout) iscompiled and a resulting bitstream is provided to the FPGA. It will alsobe appreciated by someone skilled in the art that the invention may beimplemented in the design using a VHDL routine.

[0041] Now referring to FIG. 2, there is shown two embodiments of theinvention. In a first embodiment of the invention, an electroniccomponent 8 comprises a device 10 and an aggregate device 12 comprisinga plurality of devices 10.

[0042] The device 10 and the aggregate device 12 are connected to acommon test bus 18.

[0043] The device 10 comprises a processing block 12 to test, a test busaddressing unit 14 and a test bus activation unit 16.

[0044] The processing block 12 receives an input signal and provides anoutput signal in accordance with a processing function.

[0045] In the case where the processing function is an FPGA, theprocessing function may be any one of a logic function that can beimplemented in an FPGA.

[0046] People skilled in the art will also appreciate that thisinvention may also be implemented in any reprogrammable devices such asPLD, GAL, etc. In these cases, the invention may be implemented using acorresponding programming language used normally to program thereprogrammable devices.

[0047] The test bus addressing unit 14 receives an address selectionsignal and provides an activation signal to the test bus activation unit16 if the address selection signal provided to the test bus addressingunit 14 matches the address of the device to test 10. The addressselection signal may be provided from either a device of the electroniccomponent 8 or directly from an input pad.

[0048] If the test bus activation unit 16 is activated by the activationsignal, at least one part of a processing block output data signaloutputted by the processing block 12 is outputted on the test bus 18. Inthe preferred embodiment of the invention and as explained above, atleast one of a plurality of signals located in the processing block 12is outputted on the test bus 18.

[0049] In the preferred embodiment of the invention, the test busactivation unit 16 is implemented using a threestate buffer whichoutputs the test data signal on the test bus 18 if the test busactivation unit 16 is activated by the activation signal. In anotherembodiment, the test bus activation unit 18 is implemented using amultiplexer.

[0050] It will be appreciated by someone skilled in the art that suchmethod and apparatus disclosed do not require multiple recompilings ofthe whole design.

[0051] The test bus activation units 16 as well as the test busaddressing unit 14 are inserted only at one time in the design.

[0052] As mentioned previously, the processing block 12 may be locatedin any one of an analog circuit, a digital circuit and a mixed circuit.In the case of an analog circuit or a mixed circuit, the test bus 18 maybe of the analog type. Still in such embodiment, the test bus activationunit 16 may be energized using the activation signal provided by thetest bus addressing unit 14. An amplifier may be used to provide asuitable current to the output pad.

[0053] Still referring to FIG. 2, there is also shown another embodimentof the invention, in this other embodiment, an input data activationunit 9 is provided together with a stimulus bus. The input dataactivation unit 9 receives a stimulus signal originating from saidstimulus bus. The input data activation unit 9 further receives an inputsignal for said processing unit 12. The input data activation unit 9 iscontrolled by the activation signal provided by the test bus addressing14. Upon activation, the input data activation unit 9 provides thestimulus signal to the processing block 12. The processing block outputdata signal is outputted as explained above. It will be appreciated bysomeone skilled in the art that this embodiment enables the providing ofa stimulus signal to a processing block when required.

[0054] It will be appreciated that the test bus 18 is not mandatory forproviding a stimulus signal according to this embodiment.

[0055] Now referring to FIG. 3, there is shown another alternativeembodiment of the invention, where test data signals are unclocked.

[0056] In this embodiment of the invention, a clock source 22 provides aclock signal to a plurality of devices or aggregate devices 24 to test.The plurality of devices or aggregate devices 24 to test are connectedto a test bus 26. The test bus 26 is connected to output pads 28. Theoutput pads 26 are used to output a signal from the electroniccomponent.

[0057] It will be appreciated that such unclocked test bus 26 may beused for analog and/or asynchronous circuits. The unclocked test bus 26may also be used to visualize timing information when multiple clockdomains are used.

[0058] Preferably, the embodiment shown in FIG. 3 is used when clockperiod is substantially longer than internal routing delays of theelectronic component 8.

[0059] Now referring to FIG. 4, there is shown another alternativeembodiment of the invention.

[0060] In this alternative embodiment of the invention, the electroniccomponent 8 comprises a clock source 22, a plurality of devices oraggregate devices 24, a test bus 26, memory elements 28 and output pads26.

[0061] The clock source 22 provides a clock source signal to each of theplurality of devices or aggregate devices to test 24 to test and to thememory elements 30.

[0062] Each of the plurality of devices or aggregate devices 24 to testare connected to the test bus 26. Each of the plurality of devices oraggregate devices may be selected using an address selection signal.

[0063] The test bus 26 is also connected to the memory elements 30. Thememory elements are connected to the output pads 28.

[0064] Preferably, the memory elements 30 are connected very close tothe output pads 28 in order to limit time delays.

[0065] The memory elements 28, clocked using the clock source signal areused to resynchronize test data provided by a device or aggregate deviceof the plurality of devices or aggregate devices 24 on the test bus 26with respect to the clock source 22.

[0066] Such re-synchronization is performed by the memory elements 30 inorder to provide a synchronized test data signal.

[0067] The synchronized test data signal is provided to the output pads28 by the memory elements 30.

[0068] Now referring to FIG. 5, there is shown another alternativeembodiment of the invention.

[0069] In this alternative embodiment, a plurality of clock signals 32are generated by a plurality of clock signal sources. Each of theplurality of clock signals 32 is provided to a device or aggregatedevice of a plurality of devices or aggregate devices 24.

[0070] The device or aggregate device is connected to a test bus 26. Asshown in FIG. 2, the devices or aggregate devices which may be testedand which are therefore connected to the test bus 20 each comprises thetest bus addressing unit 14 and the test bus activation unit 16.

[0071] Test data is outputted on the test bus by one selected of theplurality of devices or aggregate devices 24 using an address selectionsignal.

[0072] A multiplexer connected to memory elements 34 is used to selectone of the plurality of clock signals 32. The selected one of theplurality of clock signals 32 is selected depending on the addressselection signal used to select the device or aggregate device selectedto be tested.

[0073] This is performed in order to ensure that the test data outputtedon the test bus 26 is correctly resynchronized using a correct clocksignal. The synchronized test data signal is then provided to the outputpads 28.

[0074] Now referring to FIG. 6, there is shown another alternativeembodiment of the invention.

[0075] In this alternative embodiment, a plurality of test buses 40 areused.

[0076] More precisely at least one of a plurality of devices oraggregate devices 24 is connected to a test bus of the plurality of testbuses 40. An optional switch matrix 42 is then used to select at leastone of the plurality of test buses using a test bus selection signal.

[0077] The selected corresponding test buses provide corresponding testdata to at least one of a plurality of output pads 44. It will beappreciated by someone skilled in the art that such embodiment enables aflexible amount of output to be provided. It will be further appreciatedthat in this embodiment, the test buses 40 are unclocked. It will alsobe appreciated that each device or aggregate device of the plurality ofdevices or aggregate devices 24 does not comprise a test bus addressingunit 14.

[0078] Now referring to FIG. 7, there is shown another alternativeembodiment of the invention.

[0079] In this other alternative embodiment, a clock source 22 providesa clock source signal to a plurality of devices or aggregate devices 24to be tested.

[0080] Each of the plurality of devices or aggregate devices providestest data to a test bus of a plurality of test buses 40. Each of theplurality of test buses 40 is connected to a memory element, of aplurality of memory elements 48, clocked by the clock source 22.

[0081] Each of the plurality of memory elements 48 therefore receivestest data corresponding to a device of aggregate device of the pluralityof devices or aggregate devices 24 to test.

[0082] Synchronized test data is outputted from each of the memoryelements and provided to corresponding output pads of a plurality ofoutput pads 44.

[0083] A switch matrix 50 is alternatively used to select at least oneof the plurality of the test data originating from each of the pluralityof test buses using a test bus selection signal.

[0084] It will also be appreciated that, in this embodiment, each deviceor aggregate device of the plurality of devices or aggregate devices 24does not comprise a test bus addressing unit 14.

[0085] Now referring to FIG. 8, there is shown another alternativeembodiment of the invention.

[0086] In this other alternative embodiment, a plurality of clocksignals 32 are generated by a plurality of clock sources.

[0087] Each of the plurality of clock signals 32 is provided to a deviceor aggregate device from a plurality of devices or aggregate devices 24to test.

[0088] Each of the device or aggregate devices provides a correspondingtest data to a related test bus of a plurality of test buses 40.

[0089] A plurality of multiplexers and memory elements are used toensure that each of the related test data are synchronized using acorresponding clock signal of the plurality of clock signals 32.

[0090] Synchronized test data is provided to corresponding output padsof a plurality of output pads 44.

[0091] Alternatively, a switching matrix 48 may be used to select atleast one test bus of the plurality of test buses 40 in accordance witha test bus selection signal.

[0092] It will be appreciated by someone skilled in the art that suchselection is desirable if the number of output pads of the plurality ofoutput pads 44 is limited.

[0093] It will be appreciated that the embodiments disclosed in FIGS. 3,4, 5, 6, 7 and 8 may be adapted in the case of a providing of a stimulussignal instead of a collecting of a test data signal. It will further beappreciated that simultaneously a stimulus signal may be provided and atest data signal may be received.

[0094] It will further be appreciated that while in some embodiments thetest bus addressing unit 14 and the test bus activation unit 16 areimplemented in the device 10, in other embodiments, the test busaddressing unit 14 and the test bus activation unit 16 may beimplemented outside the device 10, in the electronic component.

[0095] The embodiments of the invention described above are intended tobe exemplary only. The scope of the invention is therefore intended tobe limited solely by the scope of the appended claims.

We claim:
 1. A method for testing a plurality of devices in anelectronic component, the method comprising the steps of: receiving aplurality of data signals from a plurality of devices to test, each ofthe plurality of devices to test receiving an input signal and providinga data signal in accordance with a device function; selecting at leastone of the received plurality of data signals in accordance with adevice selection signal; and providing the selected data signals on atest bus; whereby the selection of at least one of the receivedplurality of data signals on a test bus enables a testing of a pluralityof devices.
 2. The method as claimed in claim 1, wherein the electroniccomponent is any one of an analog circuit, a digital circuit and a mixedcircuit.
 3. The method as claimed in claim 1, wherein each of theplurality of devices is clocked, further wherein the step of providingthe selected data signals on a test bus comprising the clocking of thedata signals in accordance with the device selection signal.
 4. Themethod as claimed in claim 3, wherein the selected data signals isprovided on a plurality of test buses, each of the plurality of testbuses being clocked in accordance with a particular clock signal.
 5. Themethod as claimed in claim 1, further comprising the step of selectingbetween the providing of a stimulus signal to a device of the pluralityof devices to test and the providing of a corresponding received inputsignal to the device using a selection unit.
 6. The method as claimed inclaim 5, further comprising the step of providing a stimulus busproviding said stimulus signal to a plurality of devices, each of theplurality of devices selecting between the providing of the stimulussignal to said device and the providing of a corresponding receivedinput signal to the device using a selection unit.
 7. An apparatus fortesting at least one device in an electronic component, each of the atleast one device of the electronic component receiving an input signaland providing an output signal in accordance with a device function, theelectronic component comprising a plurality of devices, the apparatuscomprising: a data signal selecting unit, receiving a data signaloutputted from a device in response to an input signal provided to thedevice, and providing the data signal in accordance with a selectionsignal; a test bus, receiving the data signal from the data selectingunit and outputting the data signal on an output of the electroniccomponent.
 8. The apparatus as claimed in claim 7, wherein theelectronic component is any one of an analog circuit, a digital circuitand a mixed circuit.
 9. The apparatus as claimed in claim 7, wherein thedata signal selecting unit receives a plurality of data signal, eachoriginating from one of a plurality of devices of the electroniccomponent receiving an input signal, further wherein at least one of theplurality of data signal is selected in accordance with a selectionsignal and provided to the test bus.
 10. The apparatus as claimed inclaim 8, further comprising a plurality of test buses, further wherein aplurality of data signals are selected by the data signal selecting unitand provided to each of the plurality of test buses.
 11. The apparatusas claimed in claim 7, wherein the data signal selecting unit is amultiplexer, receiving the data signal from the device and providing thedata signal to the test bus using the selection signal.
 12. Theapparatus as claimed in claim 7, wherein the data signal selecting unitis a three-state buffer receiving the data signal and outputting thedata signal to the test bus using the selection signal.
 13. Theapparatus as claimed in claim 7, wherein the device is clocked using aclock signal, further comprising a time synchronization unit receivingthe data signal provided on the test bus and the clock signal andperforming a synchronization of the data signal with said clock signal.14. The apparatus as claimed in claim 7, further comprising a stimulussignal selecting unit, receiving a stimulus signal and an input signaland providing one of the stimulus signal and the input signal to adevice in accordance with a selection signal.
 15. The apparatus asclaimed in claim 14, further comprising a plurality of stimulus signalselecting units, each connected to one of a plurality of devices,further comprising a stimulus bus providing said stimulus signal to eachof the plurality of stimulus signal selecting units.